Atomic Layer Etching (ALE) & Quasichemical Nanopatterning Lab

1. The Self-Limiting Quasichemical Paradigm

As semiconductor dimensions shrink below the 2-nanometer logic node, traditional continuous plasma Reactive Ion Etching (RIE) reaches fundamental physical limitations. Continuous RIE couples radical flux and ion bombardment simultaneously, leading to severe microloading, aspect-ratio-dependent etching (ARDE), line edge roughness (LER) transfer, and crystal lattice damage. Atomic Layer Etching (ALE) resolves these challenges by subdividing the etch process into two cyclic, self-limiting half-reactions:

• Step A (Surface Functionalization / Chemisorption): The wafer is exposed to a reactive gas (e.g., molecular $\text{Cl}_2$, $\text{CHF}_3$, or anhydrous $\text{HF}$). Active surface bonding sites chemisorb a self-terminating monolayer ($\theta \to 1.0$) through Langmuir adsorption kinetics. Once all surface dangling bonds are passivated into volatile precursor complexes (e.g., $\text{SiCl}_x$ or $\text{AlF}_x$), chemical uptake halts spontaneously. Spontaneous thermal etching is zero at standard chamber temperatures ($\alpha \approx 0$).
• Purge Step 1: An ultra-high-purity inert gas pulse (Ar or $\text{N}_2$) evacuates non-adsorbed precursor molecules, eliminating gas-phase parasitic reactions.
• Step B (Desorption / Product Removal): The functionalized monolayer is selectively removed using directional low-energy $\text{Ar}^+$ ion bombardment or thermal ligand exchange. The kinetic energy is tuned strictly inside the ALE energy window ($E_{\text{th,chem}} < E_{\text{ion}} < E_{\text{th,phys}}$), desorbing the halogenated layer without sputtering underlying pristine substrate atoms ($\beta \approx 0$).
• Purge Step 2: Desorbed volatile reaction products ($\text{SiCl}_4$, $\text{Al(acac)}_3$) are pumped out to prepare the atomically pristine surface for the subsequent cycle.

2. Directional Plasma vs. Isotropic Thermal ALE

Two major technological families dominate modern ALE applications:

• Directional Plasma ALE: Employs RF substrate biasing to accelerate ions normal to the wafer surface. Unchlorinated sidewalls remain untouched, enabling anisotropic vertical profile transfer with near-infinite vertical-to-lateral selectivity. Crucial for fin trimming, Gate-All-Around (GAA) nanosheet inner spacer cavity formation, and high-aspect-ratio contact hole etching.
• Isotropic Thermal ALE: Uses sequential thermal gas exposures (e.g., fluorination followed by metal ligand exchange or metathesis) without any charged particle bombardment. Removes material uniformly in all spatial directions, making it ideal for conformal nanosheet channel release, atomic defect stripping, and gate dielectric pinhole mitigation.

3. The ALE Synergy Parameter & Energy Window Mechanics

The operational health of an ALE process is quantified by the ALE Synergy Parameter ($S_{\text{ALE}}$):

where $\text{EPC}$ is the total Etch-Per-Cycle (typically $0.8\text{ to }1.4\,\text{\AA/cycle}$), $\alpha$ is spontaneous chemical etch depth during Step A, and $\beta$ is physical sputtering depth during Step B. Achieving $S_{\text{ALE}} > 95\%$ requires precise RF synchronization:

• Chemical Sputtering Threshold ($E_{\text{th,chem}}$): The lower energy bound, typically $15\text{ to }22\text{ eV}$ for silicon. Below this threshold, ion impact cannot overcome the surface binding energy of the halogenated species.
• Physical Sputtering Threshold ($E_{\text{th,phys}}$): The upper energy bound, typically $60\text{ to }75\text{ eV}$ for pristine silicon. Above this threshold, ions induce direct collisional sputtering of unreacted substrate atoms, causing uncontrolled erosion and loss of synergy.
• Narrow Energy Window ($\Delta E$): Operating in the $30\text{ to }45\text{ eV}$ range maximizes desorption yield while preventing subsurface lattice defects and atomic displacement cascades.

4. Fab Economics & Cleanroom Yield Protection

While ALE cycle times ($8\text{ to }15\text{ s}$) result in lower wafer throughput compared to high-power continuous RIE, the financial return is driven by wafer scrap prevention in cutting-edge 2nm and 3nm foundry nodes. In a typical 300mm logic fab processing 6,500 wafers/month valued at $18,000/wafer:

• A $2.4\%$ reduction in device scrap (achieved by eliminating channel puncture and gate oxide leakage) recovers over $33.7M in annual gross value.
• Deducting chamber operating expenses ($210k/yr for specialty halogens, turbo-pump overhauls, and RF maintenance), the net annual cash flow yields an investment payback period under 2 months.